4.7.3.5 - Machine-code and assembly operations (VB.NET)

Loads, stores and arithmetic

Assembly expresses machine instructions using readable mnemonics, but the effect of each instruction is determined by the supplied machine model.

A mnemonic is a readable instruction name, such as LOAD. The machine executes an encoded machine-code instruction; assembly gives a convenient symbolic representation. Different instruction sets can use different names and operand conventions, so use the definition supplied in the task.

The original model used throughout this lesson has an unsigned eight-bit accumulator, A, and addressed memory cells containing unsigned eight-bit values. A holds a working value. The program counter, PC, identifies the next instruction. Program labels identify instruction locations. Data addresses are separate from those labels.

For arithmetic and bitwise instructions, #n means immediate value n; a bare data address means read that cell. STORE always uses a direct data address. Numbers in instructions are decimal unless explicitly written as bit patterns. Arithmetic keeps the low eight bits, so addition or subtraction wraps modulo 256. This stated convention belongs to our model, not every possible processor.

If memory[20] = 7 and memory[21] = 4, this program stores 9 in memory[22]:

LOAD 20
ADD 21
SUB #2
STORE 22
HALT

A successively becomes 7, 11 and 9. STORE 22 copies 9 to memory[22] rather than adding 22 or clearing A. LOAD #20 instead of LOAD 20 would start at 20 and change the result. After each ordinary instruction, PC advances to the next instruction; the last instruction stops the machine.

Comparisons, branches and loops

Branches change which instruction executes next, allowing an assembly program to select a path or repeat a sequence.

Our model has a comparison flag F. CMP operand compares the current unsigned A with the operand: F becomes −1 if A is smaller, 0 if equal and 1 if larger. CMP leaves A unchanged. Only CMP changes F in this model; loading, arithmetic, storage and shifts do not update it. This explicit rule prevents us from guessing that a processor's real flags behave the same way.

The comparison and branch are separate actions. In CMP #8 followed by BLT small, A is compared with value 8 and the branch tests the saved comparison result. CMP 8 would instead compare A with memory[8]. A conditional branch that is not taken does not halt: execution falls through to the next instruction.

This countdown starts at 3 and stops when the direct memory counter reaches zero:

        LOAD #3
        STORE 30
loop:   LOAD 30
        CMP #0
        BEQ done
        SUB #1
        STORE 30
        BRA loop
done:   HALT

The values stored after subtraction are 2, 1 and 0. The next comparison sees zero, so BEQ done is taken before another subtraction. Each BRA loop returns to the load; it does not return to the initial LOAD #3. Branching to the initialisation would reset the counter and prevent termination. Omitting the zero check would eventually wrap 0 to 255 in this unsigned model.

When designing a loop, identify the initial value, the state changed each pass, the comparison, and the exit path. A correct branch target matters as much as a correct arithmetic instruction. HALT is an executed instruction, whereas reaching an arbitrary label does not automatically stop the machine.

Logical and shift operations

Bitwise instructions operate on corresponding individual bits rather than treating the whole word as a true-or-false condition.

In our supplied model AND operand, OR operand and XOR operand combine A with the operand and replace A. They accept immediate values or direct memory addresses. NOT takes no operand and reverses every bit of the eight-bit A.

For A = 10100110 and operand = 00001111, AND produces 00000110, OR produces 10101111, and XOR produces 10101001. Applying NOT to the original A produces 01011001. These are four separate examples starting from the original A, not a sequence of instructions.