4.7.3.3–4.7.3.4 - Instruction sets and addressing modes

Processor-specific instruction sets

An instruction is meaningful only when the processor has rules for interpreting its bit pattern.

An instruction set is processor specific. It defines available operations, instruction formats, register use and the meanings of the encoded fields. A binary pattern understood as addition by one processor might mean something different, or be invalid, on another. Processors implementing the same instruction-set architecture may be compatible even if their internal construction differs; the point is the interpretation they implement, rather than the brand name on the computer.

Useful instruction groups include data transfer, arithmetic, logical operations and control flow. A load transfers a value into a register; a store transfers a value out to a destination. Addition and subtraction operate on values. Logical operations work on bits or conditions. Branch instructions change the next instruction address instead of leaving execution to continue at the next sequential address. These examples explain what an instruction set makes possible; the separate assembly-operations lesson develops particular operations in full.

Machine code encodes these requests as bits. An assembly-language mnemonic is a readable name associated with an operation under a particular assembler's rules. Reading a familiar mnemonic does not prove that the underlying machine-code bits are identical on two processors.

Reading operation and operand fields

An instruction contains operation information and the information needed to act on its operands.

The opcode field tells the processor which operation is requested. An instruction can have one or more operands, such as a literal value, a memory address or a register. The format tells you where the fields begin and end. Do not assume that an operand is always a number to add: it might identify the place from which that number must be obtained.

In the simple model for this specification, addressing-mode information is included in the bits allocated to the opcode. The opcode therefore identifies both the basic operation and how an operand should be interpreted. You will interpret the supplied encoding in a question; there is no universal binary table to memorise.

Consider this original eight-bit format: the first four bits are the opcode and the last four are the operand. Within the opcode, the first three select a basic operation and the last selects its addressing mode. For LOAD and ADD in this example, mode 0 is immediate and mode 1 is direct.

The instruction 0000 0101 loads the immediate value 5. The instruction 0001 0101 loads the contents of location 5. Their operand bits are identical, but the mode bit changes what those bits mean. All eight bits belong to the instruction: the space simply makes the two fields readable.

Four opcode bits permit $2^4=16$ distinct opcode patterns. The three basic-operation bits permit $2^3=8$ patterns, each combined with two possible mode-bit values. This does not prove that a real processor implements every possible combination. Four unsigned operand bits permit values or location identifiers from 0 to 15, under this example's rules. The instruction length is eight bits, rather than four, because it includes both fields.

Immediate and direct addressing

The addressing mode determines whether the operand is the datum itself or identifies where the datum is stored.

Use the previous encoding with memory location 5 holding 12. 0000 0101 loads 5 because immediate addressing uses the operand itself. 0001 0101 loads 12 because direct addressing selects location 5 and uses its contents. It does not load the address 5, and it does not follow the value 12 to another location. Following a second address is outside these two addressing modes.

In a register-addressed model, a direct operand could instead identify register 5. If that register holds 9, the datum is 9. A task must say whether an address identifies memory or a register. This is why the supplied machine rules and register/memory table matter more than guessing from a decimal operand.

Immediate addressing is useful for a constant embedded in the instruction. To use a different immediate constant, the instruction's encoded operand must change. Direct addressing lets the same instruction refer to a stored datum whose contents can change independently. A direct main-memory data access requires an additional transfer during execution; immediate data is already in the fetched instruction. This is an execution-stage distinction, not a claim that immediate instructions require no instruction fetch.

For example, suppose ACC initially holds 3 and memory[6] holds 10. ADD immediate 6 produces 9; ADD direct 6 produces 13. The basic operation is still addition in both cases. Only the source of the added datum changes. Do not treat the mode bit as an extra digit of the operand or change the operation just because data came from memory.