4.7.3.1–4.7.3.2 - Processor registers and the fetch-execute cycle

Arithmetic, control and timing

The processor combines a unit that operates on values with a unit that coordinates the work.

The arithmetic logic unit (ALU) performs arithmetic such as addition and logical operations such as AND or comparison. It receives operands and produces a result; it does not decide the whole order of the program. The control unit (CU) decodes the current instruction and issues the control signals that coordinate the ALU, registers, memory and other components. For a load instruction, for example, it arranges a memory read and a transfer into the selected register.

The clock supplies regular timing pulses that synchronise processor operations. Different stages or transfers occur in a controlled timing sequence. A clock pulse is not necessarily a whole instruction: an instruction can need several cycles, and different instructions can need different amounts of work. Clock frequency measures cycles per second.

Registers allow the processor to work on values without repeatedly retrieving every intermediate result from slower main memory. General-purpose registers can hold operands, temporary results or addresses as required by instructions. Dedicated registers have particular roles in controlling instruction execution. A register's stored bits and its role are separate: the same binary value in an address register selects a location, while in a general-purpose register it may be a number.

Dedicated register roles

Each dedicated register holds information needed for a particular stage of instruction execution.

The MAR supplies the address bus; the MBR exchanges information using the data bus. These are different jobs: a MAR value of 40 selects location 40, while an MBR value of 7 may be the data read from that location. The CIR holds the instruction, so decoding can continue while the MAR and MBR are reused to obtain its data operand.

The status flags let later instructions respond to results. A zero flag may be set when a result is zero; a conditional branch can then test it. Carry reports a carry out of a limited-width unsigned operation, whereas overflow can report a signed result outside its representable range. These flags are not synonyms, and a task must define which operations update them. Do not assume that loading data changes flags if the given machine says otherwise.

The PC is also an address, but it has a different purpose from the MAR. A data read changes the MAR without making that data location the next instruction. Saving the PC preserves where execution should resume; saving other registers preserves the working values.

Tracing fetch, decode and execute

The fetch-execute cycle repeats until execution stops or changes to another task.

In fetch, the next instruction address is copied from PC to MAR. The processor issues a memory-read signal. Memory returns the selected instruction on the data bus into MBR; the instruction is copied into CIR. PC advances to the next sequential instruction address. Some processors advance it earlier in the fetch sequence; the essential requirements are to use the old address for this fetch and leave PC ready for the next one.

In decode, the control unit interprets the instruction's operation and operand information. In execute, it performs the required transfers/ALU operation. Execution might read or write memory, change a register, communicate with I/O or replace PC for a branch. The next fetch then uses the current PC.

Consider this explicitly simplified machine. Each instruction occupies one address. ACC is a general-purpose accumulator. LOAD 40 means read the data at address 40 into ACC. LOAD does not change status flags. Initially PC = 8 and ACC = 0; memory[8] contains LOAD 40 and memory[40] contains 7. Register-copy notation below describes transfers, not a programming language.

At the end, PC is still 9, CIR still contains LOAD 40, and MAR/MBR contain 40/7. Reading memory has not removed either stored value. The second memory access belongs to execution, not another instruction fetch. If the next instruction branches to address 12, executing that branch replaces PC with 12 and the next fetch comes from 12.