1.1.1 - Von Neumann and Harvard architectures

Von Neumann uses shared memory and paths

Memory organisation determines whether instructions and data compete for the same resources.

This is a stored-program design: the program's machine instructions reside in memory so the CPU can fetch and execute them. Stored-program does not mean “Von Neumann only”; Harvard designs can store programs too.

Think of a memory containing an addition instruction at address 10 and an operand at address 80. The processor first accesses location 10 to fetch the instruction, then accesses location 80 to read the data. Both transfers use the shared CPU–memory path. In the simple model, that path cannot carry an instruction fetch and a separate data read at the same instant, so they must take turns.

This competition contributes to the Von Neumann bottleneck: the rate of transfers between CPU and memory can limit processing even when the CPU's arithmetic circuitry could work faster. Raising clock frequency cannot remove the need for the memory transfers. The term describes a performance limitation, not a guarantee that every program is always memory-bound.

A shared memory also gives flexible allocation. If a workload needs more space for data and less for instructions, it can use the common address space accordingly, subject to the operating system's rules. Instructions and data are both bit patterns; the processor's operation determines how a fetched pattern is interpreted. They are not stored in the same location simultaneously merely because they share a memory system.

Harvard separates instructions and data

Separate resources let an instruction access and a data access use different paths.

The processor can fetch an instruction while reading or writing data using the other path, provided the design supports those operations concurrently. It removes that particular instruction/data path conflict; it does not make dependencies or all memory delays disappear.

[DIAGRAM: Compare shared and separate instruction/data memory paths; asset_slug: cpu-memory-paths; caption: Von Neumann shares an instruction/data path, while Harvard separates them so instruction and data access can overlap.]

The arrows in this abstract diagram indicate communication paths, including access requests and returned contents. They do not assert that program instructions must be written back to instruction memory during normal execution. The selectable explanation supplies the same comparison without depending on the image.

Return to the processor that fetches an instruction and reads an operand. In Harvard, these needs use different paths, so the next instruction can be fetched during a current instruction's data access. This can support greater throughput when memory access is the limit. The benefit comes from the separate resources, rather than from changing the arithmetic result.

Separation also allows the instruction and data memories to use different widths or technologies suited to their roles. For example, a device may keep fixed instructions in a program memory while changing measurements in data memory. The trade-off is additional paths and less flexible sharing of capacity: unused instruction-memory space is not automatically available as data storage in a pure Harvard arrangement.

Comparing the same feature in context

A useful comparison names the same feature in both designs and explains its consequence for a workload. Saying “Harvard has separate memory; Von Neumann is cheaper” does not yet establish a matched difference about memory or explain why a particular system benefits.

Consider a sensor controller that repeatedly executes fixed instructions while reading new measurements. Separate program and data paths could support an instruction fetch alongside a measurement access. If its instructions and data have different storage needs, separate memories may also be useful. The conclusion depends on that workload and the implementation, rather than on a universal “Harvard is better”.

Now consider a general-purpose system running programs with changing instruction and data sizes. A common memory/address space makes allocation more flexible. The designer must address the shared-path bottleneck, and may use caches or other techniques to reduce main-memory traffic. Both choices involve benefits and costs; explaining the mechanism supports the judgement.

For a numerical illustration of the conflict only, assume an instruction fetch occupies a path for one slot and a data read for one slot. A pure shared path needs two slots for those two transfers. Independent Harvard paths can perform them in one slot if both are ready and no other restriction applies. This does not say a whole program becomes twice as fast: calculation, control, dependencies and other accesses still take time.

Contemporary processors combine design ideas

Contemporary processors often depart from a pure single-path Von Neumann model without making the entire computer a pure Harvard system. One common arrangement has unified main memory for instructions and data, but separate instruction and data caches close to the CPU. At that cache level, the processor can use different paths for instruction fetch and data access.

Suppose an instruction is in the instruction cache and its operand is in the data cache. Both can be supplied without competing for one cache-access path. If one is missing, the required contents must still be obtained from lower memory levels. Unified main memory can remain a bottleneck, so the cache arrangement reduces particular conflicts rather than abolishing all memory constraints.

This combined arrangement is often called a modified Harvard design. Describe the organisation you mean rather than relying on the label: shared main memory, separate instruction/data caches and paths near the CPU. Cache levels and exact arrangements vary. OCR requires awareness of departures from a pure Von Neumann architecture here, rather than memorised undocumented details of a named commercial chip.

Other relevant contemporary features include multiple cores and pipelining, already explained in the performance lesson. These add concurrency and overlapping work, but are separate design decisions from whether instructions and data share memory. “Multicore” alone does not identify Harvard or Von Neumann organisation.