1.1.1 - CPU components, registers and buses

Control and calculation

The central processing unit (CPU) executes a program's machine-code instructions. Main memory holds the program and the values it works on; the CPU must obtain the relevant values before operating on them. A high-level statement such as adding two scores is eventually implemented by machine instructions supported by the processor.

The arithmetic and logic unit (ALU) performs arithmetic, such as addition and subtraction, and logical operations, such as AND and OR on bit patterns. It also supports comparisons. A comparison can establish a condition, such as whether two values are equal, which an instruction can use to decide the next action. The ALU does not decide which program instruction should run next by itself.

The control unit (CU) decodes the current instruction and sends control signals to coordinate its execution. Those signals select transfers and operations: read memory, place a value into a register, perform addition, or write a value to memory. The clock supplies timing pulses so coordinated steps occur in an orderly sequence. A pulse is not a complete instruction: an instruction can require several steps.

For example, suppose an instruction means “add the value stored at address 70 to the current total”. The CU arranges a memory read for address 70 and selects an addition operation. The ALU performs the addition once the required values arrive. Control and calculation contribute different things to the same instruction.

What the registers hold

The CPU needs to keep several different pieces of state available while an instruction is being processed.

A register's purpose depends on the kind of value it is meant to hold. Registers are not all interchangeable names for the same storage.

An address identifies a memory location; its contents are the value stored there. If location 70 contains 12, the MAR holds 70 for that access and the MDR holds 12 when the read completes. Treating 70 and 12 as interchangeable loses the distinction between where to look and what was found.

The PC and MAR both hold addresses, but for different purposes. The PC might contain 24, the next instruction address, while the MAR contains 70, the data address used by the current instruction. The CIR can keep the current instruction while the MDR is reused for that instruction's data transfer. This is why several registers are useful even during one operation.

Suppose the ACC already contains 9 and memory location 70 contains 12. An addition using location 70 obtains 12 through the MDR, the ALU combines 9 and 12, and the ACC becomes 21. The MAR's 70 remains an address, not part of the sum. Contemporary CPUs have many additional registers; this named-register model lets us reason clearly about the required transfer paths.

Addresses, data and control signals

A memory access needs communication between components as well as storage inside them.

In the simple CPU–memory model, the three bus roles separate the destination, the transferred value and the requested action.

The address bus carries the memory address from the CPU, using the MAR, to memory. It is unidirectional in this model: the CPU specifies which location to access. The data bus carries contents, which may be data or instructions. It is bidirectional because the CPU can read from memory and write to memory. The control bus carries coordination signals such as read and write; the overall bus includes signals in different directions, for example requests and acknowledgements, rather than carrying the operand itself.

For a read of location 70 containing 12, the MAR supplies 70 on the address bus. The CU issues a read signal on the control bus. Memory returns 12 along the data bus to the MDR. The address does not travel along the data bus merely because it is represented by bits too: the role of the transfer distinguishes it.

For a write of 21 to location 71, the MAR supplies 71 on the address bus and the MDR supplies 21 along the data bus towards memory. A write signal on the control bus tells memory to store that value at the selected location. Compared with a read, the data direction and control request change; the address direction does not.

The width of the address bus limits how many different addresses it can express: more address bits allow more distinct address patterns. The data bus width affects how many bits can be transferred together. These are different consequences; a wider data bus alone does not create more memory addresses.

Connecting assembly instructions to hardware

Assembly language represents machine instructions with mnemonic names and operands. An opcode specifies the operation, while an operand supplies information needed for it, such as an address. An assembler translates the mnemonics into machine code; the CPU executes that machine code, not the printed mnemonic text.

Here is an original simplified accumulator-machine example. Addresses are denary, and these instructions use direct addressing: the numeric operand names a memory location. LOAD a copies memory location a into ACC; ADD a adds its contents to ACC; STORE a copies ACC into that location. This notation is an illustrative model, not a claim that every processor uses these exact mnemonics.

LOAD 80
ADD 81
STORE 82

Initially memory[80] = 6 and memory[81] = 14. Executing LOAD 80 requires MAR = 80 and a memory read; MDR receives 6 and ACC becomes 6. ADD 81 reads 14 using MAR = 81 and MDR = 14; the ALU adds it to ACC, producing 20. STORE 82 places address 82 in MAR and value 20 in MDR, then uses a write request. Memory[82] becomes 20. Throughout, the CIR holds the current instruction and the CU coordinates the transfers.

This also explains a common error: ADD 81 adds the contents at address 81, not the number 81. An instruction with an immediate operand could add a literal value, but that is a different addressing convention and must be specified. Likewise, loading a value replaces ACC here; it does not add to the previous ACC.